VERILAT: Veri cation Using Logic Augmentation and Transformations

This paper presents a new framework for formal logic veri cation. What is depicted here is fundamentally di erent from previous approaches. In earlier appraoches, the circuit is either not changed during the veri cation process, as in OBDD or implicationbased methods, or the circuit is progressively reduced during veri cation. Whereas in our approach, we actually enlarge the circuits by adding gates during the veri cation process. Speci cally introduced here is a new technique that transforms the reference circuit as well as the circuit to be veri ed, so that the similarity between the two is progressively enhanced. This requires addition of gates to the reference circuit and/or the circuit to be veri ed. In the process, we reduce the dissimilarity between the two circuits, which makes it easier to verify the circuits. In this paper, we rst introduce a method to identify parts of the two circuits which are dissimilar. We use the number of implications that exist between the nodes of one circuit and the nodes of the other circuit as a metric of similarity. As demonstrated, this can be a very useful metric. We formulate transformations that can reduce the dissimilarity. These are performed on those parts of the circuits which are found to be dissimilar. These admissible transformations are functionality-preserving and based on certain Boolean di erence formulations. The dissimilarity reduction transformations introduce new logical relationships between the two circuits that did not previously exist. These logical relationships are extracted as new implications, which are then used to reduce the complexity of the veri cation problem. These two steps are repeated in succession until the veri cation process is complete. A complete procedure is presented which demonstrates the power of our logic veri cation technique. The concept presented in this paper can be useful in accelerating veri cation frameworks which rely on structural methods.